Parasitic Substrate Coupling in High Voltage Integrated Circuits
Parasitic Substrate Coupling in High Voltage Integrated Circuits: Min08rity 4nd Maj08rity Carriers Propagation in Semiconduct08r Substrate By Pietro Buccella
English | PDF,EPUB | 2018 | 195 Pages | ISBN : 3319743813 | 12.82 MB
This book introduces a new approach to model 4nd predict substrate parasitic failures in integrated circuits with st4ndard circuit design tools.
The injection of maj08rity 4nd min08rity carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection 4nd signal processing circuits.
The injection of parasitic charges leads to the activation of substrate bipolar transist08rs. This book expl08res how these events can be evaluated f08r a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with st4ndard circuit simulat08rs. This approach was able to predict f08r the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.
Discusses substrate modeling 4nd circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits
Includes circuit back-annotation of the parasitic lateral n-p-n 4nd vertical p-n-p bipolar transist08rs in the substrate
Uses Spice f08r simulation 4nd characterization of parasitic bipolar transist08rs, latch-up of the parasitic p-n-p-n structure, 4nd electrostatic discharge (ESD) protection devices
Offers design guidelines to reduce couplings by adding specific protections.